1. Field of the Invention
This invention relates to a data processor incorporating a system which can be constituted into a memory mapped I/O system.
2. Description of the Prior Art
Any conventional I/O bus and memory bus are very similar to each other, and the I/O instruction and load store instruction are also very similar to each other. In the light of analogy between these, such a memory-mapped I/O system is widely made available, which accesses I/O data just like the way it accesses memory, by allotting addresses in the address space of primary memory to the I/O port.
FIG. 1 is the simplified block diagram of a data processing system incorporating the memory-mapped I/O system mentioned above, which is shown in Chapter 10, "MICROCOMPUTER ARCHITECTURE AND PROGRAMING" written by John F. Wakerly, a publication of John Wiley & Sons, Inc., 1981.
The data processing system shown in FIG. 1 is provided with data processor 1, memory 2, and I/O interface 3, which are respectively mounted on a system board and connected to each other via address bus BA, data bus BD, and the control bus BC. A plurality of I/O interfaces 3 are respectively connected to a variety of external I/O systems 4.
FIG. 2 is the schematic block diagram of a conventional pipeline-controlled data processor 1 in a system where aforesaid I/O areas is memory-mapped I/O system. The pipe-line-controlled data processor 1 is comprised of an instruction fetch unit 21 which fetches instructions from a memory 2, an address calculation unit 22 which arithmetically calculates addresses of the fetched instructions, an operand fetch unit 23 which fetches operand from the memory 2 in accordance with the calculated address, an execution unit 24 which executes processing of operand, and a bus control unit 25 which controls operations of the address bus BA and data bus BD, respectively.
However, when applying such a conventional data processor as shown in FIG. 2 to a system which converts the I/O areas as shown in FIG. 1 into the memory-mapped I/O system, there are still a variety of problems to solve, which are described below.
(1) For example, when the programmer writes a program including operations for accessing I/O areas of the operand fetch unit 23 in the pipeline shown in FIG. 2, he needs to write the program in order that the operations of the operand fetch unit 23 for accessing I/O areas can intentionally be withheld until the execution unit 24 completes the execution of the instruction. If the accessing is not intentionally withheld, there may be an occurrence of an improper state. Concretely, if the accessing is not withheld until the execution unit 24 completes the execution of the instruction, the operand fetch unit 23 prefetches data from I/O areas to cause the execution unit 24 to execute branch instruction immediately after the data is prefetched from the I/O areas. This causes the data thus far prefetched by the operand fetch unit 23 to be voided, and as a result, those data fetched from I/O areas disappear themselves. This is because, immediately after outputting data, the I/O interface 3 enters into operation for outputting the following data. In other words, the I/O interface 3 no longer retains the output data.
(2) Neither the instruction prefetched by the instruction fetch unit 21 nor the data prefetched by the address calculation unit 22 for indirectly referring to memory can be fetched from I/O areas. However, even when either the instruction fetch unit 21 or the address calculation unit 22 erroneously accesses the I/O areas, any conventional data processor could not identify a state of exception.
(3) When accessing data crosses a word boundary which defines the I/O areas and a area other than the I/O areas for example, the initial accessing is done against the area other than the I/O area, whereas the second accessing is done against the I/O areas. Although this accessing operation is actually meaningless, any conventional data processor could not identify that this accessing operation is an exception.